Fpga Verification Engineer

Job Description
What You’ll Do
We are looking for a motivated individual to join our FPGA Design Team at our headquarters in Santa Clara, CA, in the heart of Silicon Valley. In this position, you will be responsible for designing test bench, simulating, and testing FPGA RTL code that forms the backbone of our next generation systems.
Create and maintain test benches in Verilog/SystemVerilog
Create BFM, RTL models for new and existing designs
Develop the verification test plans and test cases
Review the design functional coverage
Concepts and Skills:
Work with Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.
Work with Protocols using Ethernet, such as PTP, SFlow, POE, etc.
Work with Simulation software for FPGA functional verification