Principal Engineer-Asic Design (Integration)

Job Description
Job Description
As a member of Microchip’s engineering community, your primary responsibility will be to the design, integration, and verification support of the Full Chip Architecture and Full Chip Control/Data busses for an advanced ASIC or FPGA. Microchip’s designs are an SOC with various Hard and Soft IP blocks that support many industry standard protocols.
Duties &
Responsibilities
General Full Chip Integration and Support
Detailed module design and integration, performance analysis and detailed design specification creation – a large component of this position is to work with all design teams to ensure seamless integration of all components on the device.
Detailed ownership of full chip documentation of the SOC or FPGA device and/or device family.
Participate in the Verilog implementation and integration of full chip capabilities including interface support, integration of full chip busses (control and data network-on-chip) and documentation support at the full chip level.
Support full chip post-layout timing closure and verification.
Participate in the investigation &
assessment of legacy and emerging integration techniques and on-chip / off-chip network-on-chip (NOC) bus structures for both control and high-speed data paths. Overall support of the full chip register map at the chip level is required.
Improve Data &
Command processing bandwidth, reduce latencies &
increase reliability.
Support porting the design into test chips and emulation platforms
Support pre-tapeout verification and post-tapeout validation/characterization of the system designed.
Work closely with FPGA support software and Firmware engineers to resolve hardware issues and customer issues.